CAD Automation & EDA Infrastructure Engineer
Architecting production-scale automation platforms and SPICE compact modeling frameworks. Demonstrated capability in driving global model deployment and significantly shrinking measurement timelines from days to hours at Tier-1 semiconductor companies.
CAD automation engineer with deep expertise in production-scale SKILL/Python automation platforms, process design kit (PDK) architecture, and SPICE compact modeling enablement. I thrive at the intersection of software engineering and semiconductor physics, designing robust systems that scale globally.
At Infineon, I architected a unified model lifecycle platform that slashed QA cycle time from 24 hours to 3 hours, effectively eliminating manual error pathways. I also developed automated testing flows that compressed measurement cycles from 1 day down to just 30 minutes. Previously, at Siemens EDA, I drove automated migration tooling that significantly accelerated global PDK delivery cycles.
I hold a U.S. Green Card and am available for immediate relocation. Fluent in English and native in Mandarin, I have extensive experience collaborating with U.S.-based engineering leadership to execute complex initiatives in distributed, cross-functional environments.
Automated analog circuit sizing framework integrating Bayesian Optimization with the SkyWater 130nm PDK. GUI-driven simultaneous Gain/Bandwidth optimization for single MOSFET and differential pair topologies.
Gradient-based optimization engine for SkyWater 130nm BSIM4 models. Simultaneously tunes Vth0, u0, and vsat to target measurements, eliminating the iterative manual fitting loop entirely.
Comprehensive parameterized cell library for KLayout supporting Sky130 and GF180nm PDKs. Scriptable generation for MOSFETs, Resistors, and MIM capacitors with full GDS output.
A machine learning-based tool for predicting device aging and degradation (HCI/BTI). Features Predictive Analysis using trained ML models on stress data, Reliability Modeling for HCI/BTI evaluation, and automated Visualization of degradation trends.
Automated framework for extracting symmetry, matching, and routing constraints directly from analog circuit schematics to accelerate layout generation and verification.
An interactive simulation environment built around open-source SPICE engines, enabling rapid prototyping, testing, and visualization of analog circuit behaviors.
Research focus on SPAD device characterization in HV CMOS. Produced two first-author publications in peer-reviewed IEEE venues during graduate study.
Strong foundation in semiconductor physics, solid-state theory, and analytical mathematical modeling โ core underpinning for compact device modeling work.
Advanced mastery of SKILL for EDA tool integration, complex data structures, and GUI development within the Cadence environment.
Verify Badge โExpertise in coding advanced Pcells with stretching, repetition, and conditional layout logic for PDK architecture.
Verify Badge โVerified proficiency in Python algorithm design, data manipulation, and software engineering best practices.
Verify Certificate โDevelopment of high-fidelity behavioral models for SPICE simulation and analog circuit verification.
Implementing mixed-signal behavioral models to accelerate system-level simulation and verification flows.
Verify Badge โAdvanced knowledge of C++ memory management, OOP principles, and performance optimization.
Verify Certificate โHighest level of English proficiency, demonstrating ability to communicate complex ideas with native-level precision.
Verify Result โ